In integrated circuit design, great emphasis is placed on the operating speed of the circuit. A "totem pole" output is often coupled to a transistor-transistor logic (TTL) gate to decrease the gate switching time.
In its most basic form, a TTL gate, with a totem pole output comprises an input transistor (also called a phase splitter) and two output transistors. The base of the phase splitter serves as the gate input and is coupled to the output of the previous gate. The collector of the phase splitter is coupled to the base of one output transistor (upper output transistor) and the emitter is coupled to the base of the second output transistor (lower output transistor). The emitter of the upper output transistor is coupled to the collector of the lower output transistor; this node serves as the gate output. Other circuit elements are used for biasing.
The phase splitter acts as a common emitter to the upper output transistor, turning it off when the input is high, and acts as an emitter follower to the lower output transistor, turning it off when the input is low. When the gate is in a high impedance state (3-state), both output transistors are off.
The output transistors of the TTL gate and the input transistors of the following gate contain certain capacitances which must be charged and discharged before the gate can switch. The upper output transistor acts as a current source to rapidly charge the capacitance and the lower output transistor acts as a current sink to rapidly discharge the capacitance. If the capacitance can be made to charge and discharge more rapidly, the overall speed of the gate can be increased.
Circuitry currently in existence for discharging the capacitance more rapidly (during a high to low output transition) generally depends on a diode or transistor between the collector of the phase splitter and the gate output. The diode feeds some of the output current back into the phase splitter which, in turn, forces more current to the lower output transistor to discharge the capacitance. A crucial disadvantage of this method and others is that the speedup circuits generally turn off when the output voltage is above the critical measuring voltage. Another disadvantage is that the additional current flowing into the base of the phase splitter continues even after it is no longer needed, causing a wasteful increase in the power required, especially at higher frequencies. Furthermore, speedup circuits suitable for use during a high to low logic state transition may not be suitable during a 3-state to low transition.
Therefore, a need has arisen to provide a circuit for increasing the speed of both the high to low output transition and the 3-state to low output transition without decreasing power efficiency.